This application is related to Japanese Patent Application No. HEI11(1999)-180138 filed on Jun. 25, 1999, whose priority is claimed under 35 USC xc2xa7 119, the disclosure of which is incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to a heterojunction bipolar transistor usable in a MMIC (monolithic microwave integrated circuit) for a portable telephone and its manufacturing process.
2. Description of Related Art
One problem of heterojunction bipolar transistors for power supply has been a thermal runaway. The thermal runaway means a phenomenon of breakdown of a heterojunction bipolar transistor by positive feed-back of heat. During operation of the heterojunction bipolar transistor, heat is generated by a collector current. This heat increases the collector current, which further generates heat, and so on. This is the positive feed-back of heat.
For preventing the thermal runaway, it is known to change the composition ratio of aluminum in an AlGaAs emitter layer and to provide a ballast resistor.
A conventional AlGaAs/GaAs heterojunction bipolar transistor is now explained.
Japanese Unexamined Patent Publication No. HEI 7(1995)-7013 proposes a heterojunction bipolar transistor having an emitter layer of n-AlXGa1xe2x88x92XAs wherein an Al composition ratio X is larger than 0.4. According to this transistor, the emitter layer acts as an emitter and also acts as a ballast resistor, and thereby, electrons in an X-valley which have a great effective mass can be used. Consequently, electron mobility can be decreased and an emitter resistance (Re) can be effectively raised while keeping the AlXGa1xe2x88x92XAs emitter layer in a practical thickness.
However, in this transistor, since the emitter resistance (Re) is raised by adjusting the Al composition ratio X in the n-AlXGa1xe2x88x92XAs emitter layer, the emitter resistance (Re) is already high before the collector current increases and the characteristics of the transistor may be degraded.
Japanese Examined Patent Publication No. 2662039 discloses the formation of an n-GaAs resistor layer on an n-AlGaAs emitter layer, which resistor is of the same electroconductivity type as the emitter layer, has a lower impurity concentration than the emitter layer, is different from the emitter in composition, and has the action of a ballast resistance. In an example of the publication, described is a transistor provided with an AlGaAs emitter layer (of 0.25 xcexcm thickness) having an Al composition ratio of 0.3 and an n-type impurity concentration of 5xc3x971017/cm3 and an n-GaAs resistor layer (of 0.4 xcexcm thickness) having an n-type impurity concentration of 1xc3x971016/cm3.
Japanese Unexamined Patent Publication No. HEI 10(1998)-335345 proposes a transistor provided with a ballast resistance layer of a GaAs layer formed on an AlGaAs emitter layer and a GaAs carrier supply layer formed between the emitter layer and the ballast resistance layer, the carrier supply layer having such a carrier concentration that depletion does not occur at junction. According to this transistor, the ballast resistance layer prevents the thermal runaway of the transistor and the carrier supply layer prevents diffusion of electrons from the emitter layer having a high impurity concentration to the ballast resistance layer having a low impurity concentration. Consequently, the current-amplification factor xcex2 can be kept from dropping.
However, since these n-GaAs resistor layer and ballast resistance layer act as parasitic resistance, there is a problem that they deteriorate the characteristics of the heterojunction bipolar transistors.
Accordingly, the ballast resistance layer is desired to be such that the emitter resistance is low in a normal operation state, i.e., in a state where the temperature of the transistor is low, and the emitter resistance is high in a thermal runaway state, i.e., in a state where the temperature of the transistor is high.
In other words, the ballast resistance layer is desired to provide a high temperature coefficient of the emitter resistance (simply referred to as temperature coefficient hereinafter).
However, the conventional GaAs ballast resistance layers have a relatively low temperature coefficient, which is only about 0.001xc2x0 C.xe2x88x921.
Temperature characteristics of the emitter resistance (Re) were evaluated, for example, with a heterojunction bipolar transistor as shown in an example of Japanese Examined Patent Publication No. 2662039 which has a GaAs ballast resistance layer and an emitter area of 100 xcexcm2 and a transistor as proposed by Japanese Unexamined Patent Publication No. HEI10(1998)-335345 which has an emitter area of 100 xcexcm2, a ballast resistance layer of GaAs on an AlGaAs emitter layer and a GaAs carrier supply layer between the emitter layer and the ballast resistance layer, the carrier supply layer having such a carrier concentration that depletion does not take place at junction. FIG. 11 shows the temperature characteristics of the emitter resistance (Re) in these transistors. It was found that the emitter resistance (Re) changes little with temperature change and consequently acts little as negative feed-back of heat against the thermal runaway.
Japanese Unexamined Patent Publication No. HEI 6(1994)-349847 proposes a transistor which, as shown in FIG. 16, has a ballast resistance layer of an n-AlXGa1xe2x88x92XAS layer 9 instead of a GaAs layer formed on an AlGaAs emitter layer 6. This publication describes that the Al composition ratio X in the ballast resistance layer is preferably 0 less than Xxe2x89xa60.45. If the Al composition ratio X is within this range, an energy gap between conduction band valleys in the n-AlXGa1xe2x88x92XAs layer can be adjusted, so that the temperature rises in a predetermined conduction band structure, also an increased number of electrons can be thermally excited from a conduction band (xcex93 valley) where electrons have a small effective mass to higher-level conduction bands (X valley, L valley) where electrons have a large effective mass and the electron mobility decreases. Consequently, the emitter resistance of the ballast resistance layer is low before the thermal runaway occurs and is high after the thermal runaway is induced by an increased collector current. Thus the thermal runaway of the transistor can be effectively prevented. That is, the formation of such a ballast resistance layer can suppress an increase in parasitic resistance components in the transistor and prevent the thermal runaway of the transistor.
However, in these transistors, since a base electrode is formed on the p-GaAs base layer, an insulating layer of SiN, SiO or the like is typically formed on the surface of the p-GaAs base layer. There has been a problem that the characteristics of the heterojunction bipolar transistors change because of unstableness of this insulating layer.
To cope with this problem, in Extended Abstracts of the 1994 International Conference on Solid State Devices and Materials, Yokohama, 1994, pp. 613-615 (referred to Extended Abstracts hereinafter), proposed is a transistor in which a base electrode is formed not on a p-GaAs base layer but on an n-AlGaAs emitter layer on the p-GaAs base layer.
If such a construction of the base electrode formed on the n-AlGaAs emitter layer is incorporated into the construction of Japanese Unexamined Patent Publication No. HEI 6(1994)-349847 (FIG. 15), an n-Al0.3Ga0.7As emitter layer and an n-Al0.35Ga0.65As ballast resistance layer are sequentially formed on a p+GaAs base layer. Accordingly, it is necessary to expose the n-Al0.3Ga0.7As emitter layer by sequentially etching an n+-GaAs contact layer, a graded n-AlYGa1xe2x88x92YAs layer and an n-Al0.35Ga0.65As ballast resistance layer from a substrate surface side.
In this case, it is impossible to conduct a so-called selective etching so as to stop etching when the n-Al0.3Ga0.7As emitter layer is exposed. Accordingly adjustment needs to be made by controlling the etching time. For this reason, there has been a problem in that the thickness of the emitter layer varies greatly. Since the thickness of the emitter layer (typically about 50 nm) much affects base leakage current, the base resistance, current-amplification factor and stability of characteristics of the heterojunction bipolar transistor, there is a problem that it is difficult to obtain transistor having stable characteristics if the thickness of the emitter layer is not uniform. Furthermore, in the case where the emitter layer, after exposed, is partially removed by continued etching under further control of the etching time, the thickness of the emitter layer varies more greatly.
In the aforesaid Extended Abstracts, it is described that a contact layer of InGaAs is formed on the top surface of a wafer for reducing or stabilizing a contact resistance in an emitter electrode.
However, in the case where the InGaAs contact layer is formed on a GaAs layer, these layers have greatly different crystal lattice constants and consequently it is difficult to form the layers without misfit dislocation. In the case where the InGaAs contact layer is about 100 nm thick, projections and depressions of about 10 to 20 nm are generated on the surface of the InGaAs contact layer by the misfit dislocation.
In Japanese Unexamined Patent Publication No. HEI 6(1994)-349847, if the InGaAs contact layer is formed on the top surface of the wafer, the projections and depressions on the surface of the InGaAs layer remain as they are on the n-AlGaAs emitter layer through etching under the control of the etching time before the formation of the base electrode. The characteristics of the transistor become much more unstable.
Thus, according to the transistor of Japanese Unexamined Patent Publication No. HEI 6(1994)-349847, the transistor of the Extended Abstracts and a combination of these transistors, the thermal runaway can be effectively prevented. However, since the thickness of the emitter layers is not uniform, it has been difficult to manufacture transistors having stable characteristics.
As mentioned above, it has been difficult to simultaneously realize the suppression of the emitter resistance (Re) within such a range as does not cause any problem in practical use, the prevention of the thermal runaway of the transistor and the manufacture of transistors having stable characteristics.
In view of the above mentioned problems, the inventors of the present invention have found that a heterojunction bipolar transistor whose ballast resistance layer is formed of n-AlXGa1xe2x88x92XAs (Al composition ratio X:0.15xe2x89xa6Xxe2x89xa60.35) uses, for conduction of electrons, the xe2x80x9cxcex93 valley electronsxe2x80x9d in the AlGaAs ballast resistance layer which exhibit high mobility before the thermal runaway takes place, and after the thermal runaway takes place, uses the xe2x80x9cX valley electrons, L valley electronsxe2x80x9d exhibiting low mobility due to generated heat; consequently that it is possible to decrease the temperature characteristics of the emitter resistance (Re) of the transistor within such a range as does not cause practical problems while keeping the temperature characteristics in a state of negative feed-back of heat for preventing the thermal runaway caused by an increased collector current; also that a GaAs selective etching layer between the ballast resistance layer and the emitter layer allows uniform thickness for the AlGaAs emitter layer, so that controllability and reproducibility can be improved while the emitter resistance (Re) is kept small. Thus the present invention has been achieved.
Accordingly, the present invention provides a heterojunction bipolar transistor having a ballast resistance layer between an AlGaAs emitter layer and an emitter electrode, wherein the ballast resistance layer comprises n-AlXGa1xe2x88x92XAs, wherein 0 less than X less than 1, and a GaAs selective etching layer is provided between the emitter layer and the ballast resistance layer.
The present invention also provides a process for manufacturing a heterojunction bipolar transistor having a laminated structure of a GaAs collector layer, a GaAs base layer, an AlGaAs emitter layer, a GaAs selective etching layer and an n-AlXGa1xe2x88x92XAs ballast resistance layer, wherein 0 less than X less than 1, and having a collector electrode, a base electrode and an emitter electrode. The process includes the steps of:
a) forming the GaAs selective etching layer and the n-AlXGa1xe2x88x92XAs ballast resistance layer sequentially on the AlGaAs emitter layer;
b) etching the n-AlXGa1xe2x88x92XAs ballast resistance layer or the n-AlXGa1xe2x88x92XAs ballast resistance layer and the GaAs selective etching layer in a desired pattern in such a manner that etching stops in the GaAs selective etching layer; and
c) selectively etching the remaining GaAs selective etching layer in a desired pattern.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.